The present technology relates to a bus system, and more particularly, to a clock gating circuit for a bus system.
The power consumption of a bus system tends to grow larger with more masters and slaves connected, and as a result of a larger gate scale due, for example, to the introduction of a split bus protocol. Therefore, techniques have been proposed that are designed to control the supply of a clock so as to suppress the power consumption of a bus system. In a computing system using a plurality of buses, for example, a technique has been proposed to supply a clock only to the bus adapted to pass data (refer, for example, to Japanese Patent Laid-open No. 2008-305215).